1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an LCD device in which a color filter array and a TFT array are formed on one substrate.
2. Discussion of the Related Art
Recently, LCD devices have gained in popularity as flat display devices, due to advantageous characteristics such as high contrast ratio, excellent gray level, high picture quality, and low power consumption. For example, LCD devices may be used in ultra-thin display device applications, such as wall-mountable televisions. Also, LCD devices are generally light in weight and consume low power compared to CRTs (Cathode Ray Tubes), and LCD devices can be used in notebook computers operated by battery. As such, LCD devices are generally considered to be the next generation display device.
In general, an LCD device includes a thin film transistor (TFT) array substrate and a color filter array substrate. In more detail, a plurality of gate and data lines are formed on the TFT array substrate, wherein each of the gate lines is oriented perpendicularly to each of the data lines, defining a unit pixel region. A TFT and a pixel electrode are formed in each of the pixel regions. Further, the color filter array substrate includes a color filter layer and a common electrode.
In forming a LCD device, the TFT array substrate is positioned opposite the color filter array substrate, and the two substrates are bonded to each other. Then, a liquid crystal layer having dielectric anisotropy is formed between the TFT array substrate and the color filter array substrate. The color filter array substrate and the TFT array substrate are bonded to each other by a sealant, which is formed of epoxy resins. Further, a driving circuit on a PCB (Printed Circuit Board) is connected with a TCP (Tape Carrier Package) to the TFT array substrate.
In operation, a voltage is applied to a particular pixel region by switching the corresponding thin film transistor TFT formed in a particular pixel region by selecting the corresponding gate line and data line.
FIG. 1 is a plan view illustrating a related art LCD device. As illustrated in FIG. 1, a TFT array substrate 11 includes an active region 60 and a pad region 61. In the active region 60 of the TFT array substrate 11, a plurality of gate lines 12 and a plurality of data lines 15 are formed to define a plurality of pixel regions, wherein each gate line 12 is perpendicular to each data line 15. A thin film transistor (TFT) (not shown) is formed at a crossing point of the gate line 12 and the data line 15, and a pixel electrode (not shown) is formed in each pixel region.
In the pad region 61 of the TFT array substrate 11, there are a plurality of gate pads 22 and a plurality of data pads 25. The gate pads 22 extend from the gate lines 12 to apply a gate driving signal from a gate driver to each gate line 12. Also, the data pads 25 extend from the data lines 15 to apply a data driving signal from a data driver to each data line 15. Accordingly, the plurality of gate pads 22 and data pads 25 interface with respective external driving circuits. For driving the LCD device, the gate pad 22 and the data pad 25 respectively provide connection for a driving signal between the driving circuit and the gate lines 12 and data lines 15. In this case, data input signals outputted from the driving circuit are divided according to a control signal and are then supplied to the respective pixel regions.
Although not shown, a black matrix layer is formed on the active region of the color filter array substrate for selectively blocking the light such that only the pixel regions are transmissive. A color filter layer is formed on the color filter array substrate in correspondence with the pixel regions. Then, the TFT array substrate is bonded to the color filter array substrate at a predetermined interval between them, and then a liquid crystal layer is formed between the TFT array substrate and the color filter array substrate.
Light leakage may occur due to misalignment between the thin film transistor TFT array substrate and the color filter array substrate. To solve this problem, the black matrix layer is formed to cover the edge of the pixel region. However, in doing so, the aperture ratio of the LCD device is sharply lowered. In order to overcome this problem, a TOC (TFT On Color Filter) type or a COT (Color Filter On TFT) type LCD device, in which a color filter array and a TFT array are formed on one substrate, has been introduced.
FIG. 2A is a cross sectional view illustrating an active region and a gate pad region in a COT type LCD device according to the related art. FIG. 2B is a cross sectional view illustrating an active region and a data pad region in a COT type LCD device according to the related art. FIG. 3A to FIG. 3F are cross sectional views illustrating manufacturing process steps for a gate pad region of a COT type LCD device according to the related art. FIG. 4A to FIG. 4F are cross sectional views illustrating manufacturing process steps for a data pad region of a COT type LCD device according to the related art.
In the COT type LCD device, as illustrated in FIG. 2A and FIG. 2B, a substrate 111 is divided into an active region and a pad region. A color filter layer 135 and a thin film transistor TFT are formed in the active region. The pad region includes a gate pad 122 and a data pad 125. On the active region of the substrate 111, a gate line (not shown), a gate insulating layer 113, a semiconductor layer 114, a data line (not shown), source/drain electrodes 115a/115b, and a passivation layer 116 are deposited in sequence. The gate line (not shown) having a gate electrode 112a is formed at one direction on the substrate 111, and the gate insulating layer 113 is formed on an entire surface of the substrate 111 including the gate line. Then, the semiconductor layer 114 is formed on the gate insulating layer 113 above the gate electrode 112a. The data line is formed perpendicularly to the gate line, and the source/drain electrodes 115a/115b are overlapped at opposite ends of the semiconductor layer 114 relative to the gate electrode 112a. Thereafter, a passivation layer 116 is formed on the entire surface of the substrate 111 including the source/drain electrodes 115a/115b. With this structure, a thin film transistor TFT is formed by the gate electrode 112a, the gate insulating layer 113, the semiconductor layer 114, and the source/drain electrodes 115a/115b. 
In the aforementioned structure, a black matrix layer 134 is formed on the passivation layer 116 above the gate line and the data line to prevent light from being transmitted anywhere except through the pixel region. Further, an R/G/B color filter layer 135 of R/G/B is formed on the passivation layer 116 of the pixel region. Then, an overcoat layer 136 is formed on the entire surface of the substrate including the color filter layer 135 for forming a substantially uniformly planar surface on the substrate. In addition, a pixel electrode 117 is formed on the overcoat layer 136 of the pixel region, wherein the pixel electrode 117 is electrically connected with the drain electrode 115b of the TFT.
The pixel electrode 117 is in contact with the drain electrode 115b through a contact hole 118, wherein the contact hole 118 is formed by removing a portion of the passivation layer 116 and the overcoat layer 136. According to the related art, the step of removing the passivation layer 116 is done separately from the step of removing the overcoat layer 136.
The gate pad region includes the gate pad 122, the gate insulating layer 113, the passivation layer 116, the overcoat layer 136, and a first transparent conductive layer 127. The gate pad 122 extends from the gate line (not shown). Also, the gate insulating layer 113 and the passivation layer 116, which includes a first pad open region 128, are sequentially formed on the gate pad 122. Then, the overcoat layer 136 is formed on the predetermined portion of the passivation layer 116, and the first transparent conductive layer 127 is formed in contact with the gate pad 122 through the first pad open region 128.
Referring to FIG. 2B, the data pad region includes the data pad 125, the passivation layer 116, the overcoat layer 136, and a second transparent conductive layer 137. The data pad 125 extends from the data line (not shown), and the passivation layer 116, which includes a second pad open region 138, is deposited on the data pad 125. Also, the overcoat layer 136 is formed on the predetermined portion of the passivation layer 116, and the second transparent conductive layer 137 is in contact with the data pad 125 through the second pad open region 138. In this case, the pixel electrode 117 and the first/second transparent conductive layers 127/137 are formed of the same material. A sealant 140 is formed in the interface between the active region and the pad region, on the passivation layer 116, and between the overcoat layer 136 and the first/second transparent conductive layers 127/137.
A method for manufacturing the related art LCD device is described as follows. First, as illustrated in FIG. 3A and FIG. 4A, a low-resistance metal material is deposited on the transparent glass substrate 111 by sputtering, and is then patterned by photolithography, thereby forming the gate line (not shown), the gate electrode 112a, and the gate pad 122. Next, an inorganic insulating material such as silicon oxide SiOx or silicon nitride SiNx is deposited on the entire surface of the substrate 111 including the gate electrode 112a, thereby forming the gate insulating layer 113.
After that, as illustrated in FIG. 3B and FIG. 4B, an amorphous silicon layer and a low-resistance metal layer are sequentially deposited and patterned on the gate insulating layer 113, thereby forming the semiconductor layer 114, the data line (not shown), the source/drain electrodes 115a/115b, and the data pad 125. Although not shown, it is possible to form the semiconductor layer 114, the data line (not shown), the source/drain electrodes 115a/115b, and the data pad 125 by using a half-tone mask. Accordingly, the semiconductor layer 114 remains as a lower layer under the data line (not shown) and the data pad 125. Alternatively, after patterning the semiconductor layer without using the half-tone mask, a metal layer may be deposited and patterned on the semiconductor layer to form the data line, the source/drain electrodes 115a/115b, and the data pad 125. As a result, the thin film transistor TFT is formed from the structure having the gate electrode 112a, the gate insulating layer 113, the semiconductor layer 114, and the source/drain electrodes 115a/115b in the active region.
Subsequently, as illustrated in FIG. 3C and FIG. 4C, an inorganic insulating material layer is deposited on the entire surface of the substrate 111 including the source/drain electrodes 115a/115b, thereby forming the passivation layer 116. After that, the gate insulating layer 113 is selectively etched to form the first pad open region 128, and the passivation layer 116 is selectively dry-etched to form the contact hole 118 and the first/second pad open regions 128/138. In dry-etching the passivation layer 116, the source/drain metal material layers, positioned under the passivation layer 116, function as an etching stopper. The passivation layer 116 is selectively etched by the contact hole 118, thereby exposing the drain electrode 115b of the active region. The gate pad 122 is exposed in the first pad open region 128 by selectively etching the passivation layer 116 and the gate insulating layer 113. Also, the data pad 125 of the data pad region is exposed in the second pad open region 138 by selectively etching the passivation layer 116.
After that, as illustrated in FIG. 3D and FIG. 4D, an opaque organic material having a low dielectric constant is coated and patterned on the passivation layer 116, thereby forming the black matrix layer 134 to cover the TFT, the data line (not shown), and the gate line (not shown). Then, color resist is coated and patterned on the passivation layer 116 above the black matrix layer 134, according to a constant order, thereby forming the R/G/B color filter layer 135 in the pixel region. The TFT, the black matrix layer 134, and the color filter layer 135 are formed on one substrate eliminating the requirement for forming an additional black matrix layer and a color filter layer on an opposite substrate.
Subsequently, as illustrated in FIG. 3E and FIG. 4E, an organic insulating material, for example, BCB (Benzocyclobutene) or photoacryl, is coated on the entire surface of the substrate 111 including the color filter layer 135, thereby forming the overcoat layer 136. The overcoat layer 136 is formed to create a substantially planar surface on the entire substrate 111. In this respect, the overcoat layer 136 is essential to the COT type LCD device. Then, the overcoat layer 136 deposited in the contact hole 118 and in the first/second pad open region 128/138 is removed. Then, the black matrix layer 134 and the color filter layer 135 of the organic material, positioned on the contact hole 118, are removed at the same time, thereby exposing the drain electrode 115b. 
After that, as illustrated in FIG. 3F and FIG. 4F, a transparent conductive material is deposited and patterned on the passivation layer 116, thereby forming the pixel electrode 117 in each pixel region, and simultaneously forming the first and second transparent conductive layers 127 and 137 on the respective gate pad and the data pad. The pixel electrode 117 is electrically connected with the drain electrode 115b through the contact hole 118, and the first and second transparent conductive layers 127 and 137 are electrically connected with the respective gate pad 122 and the data pad 125 through the first and second open pad regions 128 and 138. Afterwards, the sealant 140 is formed in the interface between the active region and the pad region in the LCD device, wherein the sealant 140 serves as an adhesive. After that, the substrate 111 is positioned opposite to another glass substrate (not shown), and the two substrates are bonded to each other. In this state, liquid crystal is injected between the two substrates, thereby completing the LCD device.
However, the related art LCD device and its manufacturing method have the following disadvantages. Forming the contact hole in the active region and the pad open region in the pad region requires multiple process of etching the gate insulating layer and the passivation layer as well as the subsequent process of patterning the overcoat layer. Accordingly, the preceding process and the subsequent process are separately performed in different devices, thereby complicating the manufacturing process.